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dc.contributor.authorDaniela, Kaufmann-
dc.contributor.authorArmin, Biere-
dc.date.accessioned2023-03-31T02:24:57Z-
dc.date.available2023-03-31T02:24:57Z-
dc.date.issued2023-
dc.identifier.urihttps://link.springer.com/article/10.1007/s10009-022-00688-6-
dc.identifier.urihttps://dlib.phenikaa-uni.edu.vn/handle/PNK/7364-
dc.descriptionCC BYvi
dc.description.abstractVerifying arithmetic circuits and most prominently multiplier circuits is an important problem which in practice is still considered to be challenging. One of the currently most successful verification techniques relies on algebraic reasoning. In this article, we present AMULET2, a fully automatic tool for verification of integer multipliers combining SAT solving and computer algebra. Our tool models multipliers given as and-inverter graphs as a set of polynomials and applies preprocessing techniques based on elimination theory of Gröbner bases.vi
dc.language.isoenvi
dc.publisherSpringervi
dc.subjectAMULET2vi
dc.subjectSATvi
dc.titleImproving AMULET2 for verifying multiplier circuits using SAT solving and computer algebravi
dc.typeBookvi
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