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dc.contributor.authorH. H., Draz-
dc.contributor.authorN. E., Elashker-
dc.contributor.authorMervat M. A., Mahmoud-
dc.date.accessioned2023-04-18T03:10:44Z-
dc.date.available2023-04-18T03:10:44Z-
dc.date.issued2023-
dc.identifier.urihttps://link.springer.com/article/10.1007/s00034-023-02370-x-
dc.identifier.urihttps://dlib.phenikaa-uni.edu.vn/handle/PNK/8026-
dc.descriptionCC BYvi
dc.description.abstractImage processing algorithms are essential for clarifying the image and improving the ability to recognize distinct characteristics of the image. The field of digital image processing is widespread in several research and technology applications. In many of these applications, the existence of impulsive noise in the obtained images is one of the most frequent problems. The median filter is a strong method to remove the impulsive noise; it effectively eliminates salt and pepper noise from the image. The main target of this paper is to investigate efficient median filter units to be connected to a general-purpose processor (GPP) for FPGA-based embedded systems. The paper exposes three novel techniques, two of them specially for median filtering techniques and the third one is used to get the maximum number of any 9 elements array. The proposed algorithms are inspired by the Median Of Median (MOM) algorithm.vi
dc.language.isoenvi
dc.publisherSpringervi
dc.subjectFPGA-based embedded systemsvi
dc.subjectMedian Of Median (MOM) algorithmvi
dc.titleOptimized Algorithms and Hardware Implementation of Median Filter for Image Processingvi
dc.typeBookvi
Bộ sưu tậpOER - Kỹ thuật điện; Điện tử - Viễn thông

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